For the better part of two decades, control-flow hijacking has been the go-to technique for exploiting memory corruption. If you can overwrite a single code pointer—whether that’s a return address, a function pointer, or a C++ vtable slot—you can redirect execution anywhere you want, without needing to inject any custom shellcode. Intel’s Control-flow Enforcement Technology (CET) was designed to tackle this exact problem at the hardware level. It turns certain control-flow transfers into illegal operations, with the CPU enforcing these rules on the fly.

CET breaks down into two main components: a shadow stack to protect function returns, and Indirect Branch Tracking (IBT) to secure indirect calls and jumps.

In the ever-evolving landscape of computer architecture, RISC-V has emerged as a promising and disruptive force. With its open-source nature and elegant design philosophy, RISC-V has garnered significant attention from both academia and industry alike. Unlike proprietary architectures, RISC-V is an open-source instruction set architecture (ISA) that provides unrestricted access to its specifications. This openness has spurred innovation, encouraging a flourishing ecosystem of developers, researchers, and companies to contribute to its development. Recent statistics indicate a surge in the adoption of RISC-V architecture, serving as a testament to its growing popularity. According to industry reports, the shipment of RISC-V-based devices reached an astounding 1 billion units in 2022 alone, marking a significant milestone for this emerging technology.

In the past few months I did some webinar on ARM architecture and shellcode, I thought it would be good idea to create a post which has links to all of those webinars.

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